This work aims at the realization of a high-level environment to facilitate and accelerate the neural network implementation on FPGAs. A parameterizable tool was designed to generate a neural multi-layer network implementation through the use of Handel-C language. The algorithm used for the training is the back-propagation. The tools of implementation and synthesis are the DK of Celoxica and the ISE of Xilinx. The targeted components are XCV2000 on Celoxica RC1000 board and XC2V1000 on RC200. Experimental evaluations are presented to demonstrate the validity of the design.
|International Review of Electrical Engineering
|Published - 31 Dec 2009