An FPGA implementation of a Feed-Back Chaotic Synchronization for secure communications

Mohamed Azzaz, Camel Tanougast, Said Sadoudi, Ahmed Bouridane, A. Dandache

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

13 Citations (Scopus)

Abstract

In this paper, we propose a hardware implementation of a Feed-Back Chaotic Synchronization (FCS) for designing a real-time secure symmetric encryption scheme. This proposed scheme allows for the design and implementation of real time synchronization between two embedded chaotic generators for secure communications. The implementation and experimental results mapped on two Xilinx FPGA Virtex technology platforms using two Lorenz three-dimensional continuous chaotic systems demonstrate the feasibility and the usefulness of this synchronization approach in terms of performance and hardware resources for embedded encryption systems.
Original languageEnglish
Title of host publicationCommunication Systems Networks and Digital Signal Processing (CSNDSP), 2010 7th International Symposium on
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages239-243
ISBN (Print)978-1-4244-8858-2
Publication statusPublished - 2010

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