Increasing the power conversion efficiency (PCE) of kesterite Cu2ZnSn(S,Se)4 (CZTSSe) solar cells has remained challenging over the past decade, in part due to open-circuit voltage (VOC)-limiting defect states at the absorber/buffer interface. Previously, we found that substituting the conventional CdS buffer layer with In2S3 in CZTSSe devices fabricated from nanoparticle inks produced an increase in the apparent doping density of the CZTSSe film and a higher built-in voltage arising from a more favorable energy-band alignment at the absorber/buffer interface. However, any associated gain in VOC was negated by the introduction of photoactive defects at the interface. This present study incorporates a hybrid Cd/In dual buffer in CZTSSe devices that demonstrate an average relative increase of 11.5% in PCE compared to CZTSSe devices with a standard CdS buffer. Current density–voltage analysis using a double-diode model revealed the presence of (i) a large recombination current in the quasi-neutral region (QNR) of the CZTSSe absorber in the standard CdS-based device, (ii) a large recombination current in the space-charge region (SCR) of the hybrid buffer CZTSSe–In2S3–CdS device, and (iii) reduced recombination currents in both the QNR and SCR of the CZTSSe–CdS–In2S3 device. This accounts for a notable 9.0% average increase in the short-circuit current density (JSC) observed in CZTSSe–CdS–In2S3 in comparison to the CdS-only CZTSSe solar cells. Energy-dispersive X-ray, secondary-ion mass spectroscopy, and grazing-incidence X-ray diffraction compositional analysis of the CZTSSe layer in the three types of kesterite solar cells suggest that there is diffusion of elemental In and Cd into the absorbers with a hybrid buffer. Enhanced Cd diffusion concomitant with a double postdeposition heat treatment of the hybrid buffer layers in the CZTSSe–CdS–In2S3 device increases carrier collection and extraction and boosts JSC. This is evidenced by electron-beam-induced current measurements, where higher current generation and collection near to the p–n junction is observed, accounting for the increase in JSC in this device. It is expected that optimization of the heat treatment of the hybrid buffer layers will lead to further improvements in the device performance.