Optimization techniques for designing analogue CMOS circuits within a high-level synthesis system

D. Enright; I. Rosena; R. J. Mack; R. E. Massara; R. J. Binns; P. Hallam

Optimization techniques for designing analogue CMOS circuits within a high-level synthesis system

D. Enright^*, I. Rosena, R. J. Mack, R. E. Massara, R. J. Binns, P. Hallam

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

The role of circuit-level optimization within an analogue synthesis system is described. Alternative strategies are presented, ranging from optimization guided by sensitivity to the incorporation of design equations. A sequential strategy is discussed, which partitions the problem into several phases rather than attempting to meet all the design goals in a single stage of optimization. Results are presented, comparing the accuracy and speed of the alternative strategies, for the design of a CMOS operational amplifier.

Original language	English
Pages	225-228
Number of pages	4
Publication status	Published - 1999
Externally published	Yes
Event	8th International Symposium on Integrated Circuits, Devices and Systems, ISIC 99 - Singapore, Singapore Duration: 8 Sept 1999 → 10 Sept 1999

Conference

Conference	8th International Symposium on Integrated Circuits, Devices and Systems, ISIC 99
Country/Territory	Singapore
City	Singapore
Period	8/09/99 → 10/09/99

Cite this

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title = "Optimization techniques for designing analogue CMOS circuits within a high-level synthesis system",

abstract = "The role of circuit-level optimization within an analogue synthesis system is described. Alternative strategies are presented, ranging from optimization guided by sensitivity to the incorporation of design equations. A sequential strategy is discussed, which partitions the problem into several phases rather than attempting to meet all the design goals in a single stage of optimization. Results are presented, comparing the accuracy and speed of the alternative strategies, for the design of a CMOS operational amplifier.",

author = "D. Enright and I. Rosena and Mack, {R. J.} and Massara, {R. E.} and Binns, {R. J.} and P. Hallam",

year = "1999",

language = "English",

pages = "225--228",

note = "8th International Symposium on Integrated Circuits, Devices and Systems, ISIC 99 ; Conference date: 08-09-1999 Through 10-09-1999",

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T1 - Optimization techniques for designing analogue CMOS circuits within a high-level synthesis system

AU - Enright, D.

AU - Rosena, I.

AU - Mack, R. J.

AU - Massara, R. E.

AU - Binns, R. J.

AU - Hallam, P.

PY - 1999

Y1 - 1999

N2 - The role of circuit-level optimization within an analogue synthesis system is described. Alternative strategies are presented, ranging from optimization guided by sensitivity to the incorporation of design equations. A sequential strategy is discussed, which partitions the problem into several phases rather than attempting to meet all the design goals in a single stage of optimization. Results are presented, comparing the accuracy and speed of the alternative strategies, for the design of a CMOS operational amplifier.

AB - The role of circuit-level optimization within an analogue synthesis system is described. Alternative strategies are presented, ranging from optimization guided by sensitivity to the incorporation of design equations. A sequential strategy is discussed, which partitions the problem into several phases rather than attempting to meet all the design goals in a single stage of optimization. Results are presented, comparing the accuracy and speed of the alternative strategies, for the design of a CMOS operational amplifier.

UR - http://www.scopus.com/inward/record.url?scp=1842728420&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:1842728420

SP - 225

EP - 228

T2 - 8th International Symposium on Integrated Circuits, Devices and Systems, ISIC 99

Y2 - 8 September 1999 through 10 September 1999

ER -

Optimization techniques for designing analogue CMOS circuits within a high-level synthesis system

Abstract

Conference

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Cite this