Abstract
The role of circuit-level optimization within an analogue synthesis system is described. Alternative strategies are presented, ranging from optimization guided by sensitivity to the incorporation of design equations. A sequential strategy is discussed, which partitions the problem into several phases rather than attempting to meet all the design goals in a single stage of optimization. Results are presented, comparing the accuracy and speed of the alternative strategies, for the design of a CMOS operational amplifier.
| Original language | English |
|---|---|
| Pages | 225-228 |
| Number of pages | 4 |
| Publication status | Published - 1999 |
| Event | 8th International Symposium on Integrated Circuits, Devices and Systems, ISIC 99 - Singapore, Singapore Duration: 8 Sept 1999 → 10 Sept 1999 |
Conference
| Conference | 8th International Symposium on Integrated Circuits, Devices and Systems, ISIC 99 |
|---|---|
| Country/Territory | Singapore |
| City | Singapore |
| Period | 8/09/99 → 10/09/99 |
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