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Optimization techniques for designing analogue CMOS circuits within a high-level synthesis system

D. Enright*, I. Rosena, R. J. Mack, R. E. Massara, R. J. Binns, P. Hallam

*Corresponding author for this work

    Research output: Contribution to conferencePaperpeer-review

    2 Citations (Scopus)

    Abstract

    The role of circuit-level optimization within an analogue synthesis system is described. Alternative strategies are presented, ranging from optimization guided by sensitivity to the incorporation of design equations. A sequential strategy is discussed, which partitions the problem into several phases rather than attempting to meet all the design goals in a single stage of optimization. Results are presented, comparing the accuracy and speed of the alternative strategies, for the design of a CMOS operational amplifier.

    Original languageEnglish
    Pages225-228
    Number of pages4
    Publication statusPublished - 1999
    Event8th International Symposium on Integrated Circuits, Devices and Systems, ISIC 99 - Singapore, Singapore
    Duration: 8 Sept 199910 Sept 1999

    Conference

    Conference8th International Symposium on Integrated Circuits, Devices and Systems, ISIC 99
    Country/TerritorySingapore
    CitySingapore
    Period8/09/9910/09/99

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