Performance characteristics of cascaded delay-line node architectures in single-path interconnection networks

Internally buffered multistage interconnection network architectures have been widely used in parallel computer systems and large switching fabrics. Migration from electrical domain to optical domain has raised the necessity of developing node architectures with optical buffers. Cascaded fibre delay line architectures can be seen as possible realizations of output and shared buffering in a 2 × 2-switching element. These approaches can be used as buffered node architecture in a Banyan like interconnect. In this paper, we investigate and compare these approaches by using simulation methods. Different performance metrics, such as normalized throughput, average packet delay, packet loss rate and buffer utilization have been used under uniform and non-uniform traffic models. Results show that the TC-chain node Banyan network offer an improved normalized throughput and average packet delay performances under both traffic models without disrupting first-in-first-out order of arrivals. The switched delay-line requires fewer switching elements than TC and TTC architectures but at the cost of high packet delay.