TY - JOUR
T1 - Threshold temperature scaling
T2 - Heuristic to address temperature and power issues in MPSoCs
AU - Shehzad, Muhammad Naeem
AU - Bashir, Qaisar
AU - Farooq, Umer
AU - Ahmed, Ghufran
AU - Raza, Mohsin
AU - Kumar, Priyan Malarvizhi
AU - Khalid, Muhammad
PY - 2020/9/1
Y1 - 2020/9/1
N2 - In this article, we propose a scheduling based temperature and power-aware heuristic for multi-core systems. Instead of using a fixed value of temperature threshold in load balancing techniques, the proposed heuristic suggests adjusting the value of threshold temperature as a function of the workload. As the workload reduces, the value of the threshold is lowered accordingly and vice versa. Lowering the value of threshold temperature decreases the temperature peaks, temperature spatial, and temporal gradients. Furthermore, it also reduces the total power consumed by the processing unit. The effectiveness of the approach is evaluated in a simulation-based environment that includes a scheduling and a thermal modeling tool. For evaluation, the heuristic is integrated with a state of the art load balancing technique based on global scheduling and a comparison is performed with the popular thermal-aware techniques. The results analysis shows that the use of proposed heuristic lowers the temperature peak by up to 7 °C, temperature spatial gradients by up to 35%, temporal gradient by 65%, and power utilization by up to 5.5% when compared with the state-of-the-art thermal balancing techniques and predictive thermal-aware models.
AB - In this article, we propose a scheduling based temperature and power-aware heuristic for multi-core systems. Instead of using a fixed value of temperature threshold in load balancing techniques, the proposed heuristic suggests adjusting the value of threshold temperature as a function of the workload. As the workload reduces, the value of the threshold is lowered accordingly and vice versa. Lowering the value of threshold temperature decreases the temperature peaks, temperature spatial, and temporal gradients. Furthermore, it also reduces the total power consumed by the processing unit. The effectiveness of the approach is evaluated in a simulation-based environment that includes a scheduling and a thermal modeling tool. For evaluation, the heuristic is integrated with a state of the art load balancing technique based on global scheduling and a comparison is performed with the popular thermal-aware techniques. The results analysis shows that the use of proposed heuristic lowers the temperature peak by up to 7 °C, temperature spatial gradients by up to 35%, temporal gradient by 65%, and power utilization by up to 5.5% when compared with the state-of-the-art thermal balancing techniques and predictive thermal-aware models.
KW - Embedded systems
KW - Multi-core systems
KW - Scheduling algorithm
KW - Temperature threshold
KW - Thermal management
UR - http://www.scopus.com/inward/record.url?scp=85085947201&partnerID=8YFLogxK
U2 - 10.1016/j.micpro.2020.103124
DO - 10.1016/j.micpro.2020.103124
M3 - Article
AN - SCOPUS:85085947201
SN - 0141-9331
VL - 77
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
M1 - 103124
ER -